System for and method of efficiently controlling memory accesses in a multiprocessor computer system

ABSTRACT

A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

RELATED APPLICATIONS

This is a continuation of application Ser. No. 08/794,479 filed Feb. 4,1997, now abandoned, which is a continuation of application(s) Ser. No.08/342,131 filed on Nov. 18, 1994, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to computer systems havingmultiple processors with caches. In particular, the present inventionrelates to a system and method for implementing cache tags in a memoryfor maintaining cache coherence.

2. Description of the Background Art

The use of multiple processors is a recent trend in computer design.Each processor may work on a separate portion of a problem, or work ondifferent problems, simultaneously. The processors used in themulti-processor architectures generally each have cache. A cache is arelatively small group, when compared to shared memories, of high speedmemory cells that are specifically dedicated to a processor. Aprocessor's cache is usually on the processor chip itself or may be onseparate chips.

Processors use caches to hold data that the processor has recentlyaccessed. A memory access is any action, such as a read or a write,where a processor receives, modifies, or receives as well as modifiesthe contents of a memory location. Generally, a processor can accessdata in its cache faster than it can access data in the main memory ofthe computer. Furthermore, by using data in its cache, a processor doesnot use the bus of the computer system to access data. This leaves thebus free for use by other processors and devices.

A particular problem associated with the use of caches is that the databecomes “stale.” A first processor may access data in the main memoryand copy the data into its cache. The first processor may then modifythe data in its cache. At the instant when the data in the cache of thefirst processor is modified, the corresponding data in the memory isstale. If a second processor subsequently accesses the original data inthe main memory, the second processor does not find the most currentversion of the data. The most current version is in the cache of thefirst processor. The second processor, however, needs the most currentversion of the data. A prior art solution to this problem is forprocessors to eavesdrop on the bus. When the first processor detects themain memory access by the second processor for data that the firstprocessor holds in its cache, the first processor inhibits the mainmemory and supplies the data to the second processor. In this way, aprocessor always receives the most current version of the data.

This prior art solution suffers from a number of problems. Computerarchitectures are moving to multiple-processor, multiple-busconfigurations. The busses are coupled through an interface. Forefficiency purposes, many signals on a bus are not transmitted acrossthe interface to other busses. Among signals, which are not transmittedacross the interface, are memory access signals where the path betweensource and target devices does not cross the interface. Many otherdevices also do not transmit all signals that they receive. For example,cross-bar switches, which concurrently connect multiple pairs of sourceand target ports, limit the transmission of memory access signals to thedata path between source and target. When devices do not transmit allmemory access signals over its data path, it is impossible forprocessors, which are not the source and target, to eavesdrop on memoryaccesses and therefore, impossible to determine when the data is stale.Thus, this prior art solution is not effective in systems that usedevices that do not transmit all memory access signals.

Decreases in access time of main memories and increases in the size ofcaches have created other problems with eavesdropping. Eavesdropping onthe bus assumes that a processor can inhibit the main memory and placethe data on the bus faster than the main memory can access the data.Memories may, however, cache copies of recently accessed data withinthemselves; in which case, they often can provide data before aprocessor can inhibit the memory. Also, caches have become larger.Generally, larger memories, whether main memories or caches, requiremore time to access. Processors, with large caches, cannot access thelarger cache fast enough to make the prior art solution workable unlessother memory access are delayed while eavesdropping is performed. Such adelay would significantly degrade the performance of the processor.

Memory tags have been used to overcome some of these problems. A memorytag is associated with a memory address whose data is held in a cache.When a processor copies the data at that address into its cache, amemory tag is updated to identify the processor in whose cache the datais held. If a second processor attempts to access the data in thememory, the processor will receive the memory tag. Memory tags removethe need for eavesdropping. The memory tags are held in a separatememory device called a tag storage. When a processor reads or writesdata to a memory address, both the tag storage and the memory addressare accessed. The memory address is accessed for the data, and the tagstorage is accessed for the possibility of a memory tag. If the accessesare performed sequentially, two accesses greatly slow the operation ofthe memory. If done in parallel, the tag storage greatly complicates thedesign of the memory controller. The width of the tag storage differsfrom the width of the main memory, in one embodiment the tag storage is20 bits wide and the main memory is 64 bits wide. The different sizedmemories require complicated modifications to the memory controller.Furthermore, the tag storage requires changes in the bus width andrequires additional circuit chips that occupy space, consume power, andadd to the expense of the computer system.

Referring now to FIG. 1, a block diagram of a prior art memory 23 isshown. The prior art memory 23 comprises a data storage 40, a tagstorage 42, and a memory controller 25. The data storage 40 comprises aplurality of memory lines. Each memory line comprises one or more wordsand has an unique address. A first memory line 44 has address 0, and asecond memory line 46 has address 1. Each address indicates a completememory line. The remaining memory lines of the data storage 40 areaddressed similarly so that a last memory line 48 has address N−1, whereN is the total number of memory lines in the data storage 40. Each wordhas a fixed bit size. A word may be any number of bits long, butcurrently is preferably 64 bits long or other powers of 2. A memory line44, 46, 48 may include any number of words, but within the data storage40 each memory line 44, 46, 48 has the same number of words. The tagstorage 42 comprises a tag cell for each memory line of the data storage40. Each tag cell has an address that corresponds to a memory line ofthe data storage 40. A tag cell 50 has an address 0 and corresponds tothe first memory line 44. Similarly, a tag cell 52 has an address 1 andcorresponds to a second memory line 46, and a tag cell 54 has addressN−1 and corresponds to a final memory line 48. Each tag cell 50, 52, 54is more than one bit wide and contains data that indicates if the dataheld in the corresponding memory line 44, 46, 48 is valid data or if aprocessor holds the data. Data is valid, or “fresh,” if no processorholds the data in its cache. Fresh data may also be referred to as“unowned” data. Data is referred to in this application as “owned” andis not fresh if a processor holds a copy of the data in its cache. If aprocessor owns the data, the tag cell 50, 52, 54 contains an indicatorfor indicating that the data is owned and a tag that identifies theprocessor that owns the data.

Any memory operation that requires the data held at an address isreferred to as an access. The basic operations are ReadOwned andWriteReturn. ReadOwned and WriteReturn will be discussed in detailbelow. Other operations may also be performed. The processor that isexecuting an operation is referred to as the accessing processor. Everymemory access requires an operation on the addressed memory line 44, 46,48 and the assigned tag cell 50, 52, 54. This is true whether the memoryaccess is a ReadOwned or a WriteReturn. If the access is a ReadOwned,the data storage 40 must be read, and the tag storage 42 must be read todetermine if the data is fresh. If the memory access is a WriteReturn,the appropriate address must be written to and the assigned tag cell 50,52, 54 must be set to indicate fresh data.

The memory controller 25 is a state machine for controlling theoperation of the memory 23. The memory controller 25 is coupled toprocessors and other devices of a computer system by a bus 31. Data,control, and address signals are transmitted to the memory 23 on the bus31. The memory controller is coupled to the data storage 40 by a line 27and is coupled to the tag storage 42 by a line 29. In this application,a line refers to one or more wires. When the memory controller 25receives a memory access signal, it must perform an operation on boththe data storage 40 and the tag storage 42. For example, if the memorycontroller 25 receives a ReadOwned command on the bus 31 for a memorylocation in the data storage 40, the memory controller 25 first assertsa signal on line 27 for the data storage 40 to transmit the contents ofthe first memory line 44 to the memory controller 25. For purposes ofthis example, it will be assumed that the memory address was 0 for thefirst memory line 44. The data storage transmits the data on line 27.The memory controller 25 simultaneously asserts a signal on line 29 forthe tag storage 42 to transmit the contents of tag cell 50 to the memorycontroller 25. The memory controller 25 determines if the data, receivedfrom the tag storage 42, indicates that the data contained in memoryline 44 is owned. If the data contained in memory line 44 is unowned,the memory controller outputs the data onto the bus 31. If the data isowned, the memory controller 25 outputs the tag contained in the tagcell 50. Other memory accesses such as WriteReturn also require anoperation on both the data storage 40 and the tag storage 42. This priorart memory 23 is slow and requires more complicated memory controllerlines 27, 29.

As can be seen from the above example, there is a continuing need for afaster system and method for ensuring that processors receive fresh dataand for identifying processors holding cached data. This system andmethod should not require modifications to other devices of a computersystem.

SUMMARY OF THE INVENTION

The present invention overcomes the deficiencies and limitations of theprior art with a system and method for controlling memory accesses in amulti-processor computer system. The present invention advantageouslyprovides a system for storing data that identifies valid data andidentifies data held in a processor's cache without a separate tagstorage. The present invention also advantageously reduces the number ofread functions that must be executed to access a memory location.

The system comprises a data storage device and a memory controller. Thedata storage device comprises a plurality of memory lines, each memoryline having an unique address. A memory line comprises one or more 64bit words. Words having any number of bits, however, may be used. Eachmemory line comprises a check field, a g bit field, a tag field, and adata field. A small portion of the data storage is used for a pluralityof d bit fields. Each memory line in the remaining portion of the datastorage has an assigned d bit field. A memory line may contain data orcodes; the codes indicate that a processor owns the data in the cache.

When a memory line contains unowned data, the data resides in the memoryline as in a conventional memory device. The check field, g bit field,and tag field are used to hold the data along with the rest of thememory line.

When the memory line contains owned data, the data resides in a cache ofa processor. The check field and tag fields contain codes; the checkfield code contains a GONE code and the tag field code is a encodedidentifier of the processor that holds the data. Thus, on each memoryaccess, the data is output, or the location of the data in a cache isoutput. As opposed to the prior art, a second memory access is generallynot required. A special case occurs, however, when data is being held ina memory line that happens by chance to have a check field equal toGONE. In this case, the data in the data storage is unowned, but itappears that the data is owned. For this rare situation, the presentinvention advantageously uses a g bit field. The g bit field contains aG bit. Whenever the data is owned, the G bit is set to 1. If the data isin the memory line, but the data in the check field by chance matchesthe GONE value, the G bit is set to 0 and the actual data value,normally held in the g bit field, is contained in the assigned d bitfield. Thus, there are three cases: 1) The data is owned. In this case,the check field code is GONE, the g bit field contains a 1, and the tagfield contains an indicator of the processor that owns the data; 2) Thedata is unowned, and the data contained in the check field portion ofthe memory line does not match the GONE code for identifying owned data.In this case the memory line contains the data; and 3) The data iscontained in the memory line, and the data held in the check fieldportion of the memory line matches the GONE code. In this case, the gbit field holds a 0 and the d bit field holds the true value of the Gbit.

As can be seen, only in the rare third case is a second memory accessrequired to obtain the requisite data. For any memory line, the GONEcode may be any value but is preferably the result of a hashing functionof the address of the memory line.

The memory controller comprises a data buffer, an address buffer, and amemory sequencer. The data buffer receives data signals and outputs datasignals for the memory device. Similarly, the address buffer receivesaddress signals for the memory device. The memory sequencer is a statemachine that receives control signals, compares data received by thedata buffer to data stored in the data storage, and generates signals tocontrol the operation of the memory device.

The present invention includes a method for implementing cache tags formulti-processor computer systems. The method includes the steps ofreading a memory line; determining if the data contained in a checkfield portion of the memory line matches a GONE code generated from theaddress of the memory line; if the GONE code and data do not match,reading the data as data; if the GONE code and data match, checking a Gbit; if the G bit is 1, outputting the address of the processor thatholds the data in its cache; and if the G bit is 0, reconstructing thedata from a D bit and outputting the data as data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art system of a main memory and amemory for storing memory tags that identify processors holding data;

FIG. 2 is a block diagram of an exemplary multi-processor, multi-buscomputer system;

FIG. 3 is a block diagram of a memory constructed according to thepresent invention;

FIG. 4 is a block diagram of a second embodiment of a memory constructedaccording to the present invention;

FIG. 5 is a block diagram of the second embodiment of the memory andassociated control circuitry constructed according to the presentinvention;

FIG. 6 is a state diagram of the states of a memory sequencer of thepresent invention; and

FIGS. 7A, 7B, and 7C are flow charts showing a method for accessing amemory device according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 2, a block diagram of a computer system 10 isshown. While the system 10 will now be described with reference to 4processors, those skilled in the art will realize that the presentinvention applies to any system having a plurality of processors. Thecomputer system 10 comprises a first processor 12, a second processor14, a third processor 16, a fourth processor 18, and a memory 20. Thefirst processor 12, a second processor 14, and memory 20 are coupled bya first bus 22, and the third processor 16 and fourth processor 18 arecoupled by a second bus 24. The first bus 22 and the second bus 24 arecoupled by an A interface 26 and a B interface 28. The A interface 26 iscoupled to the first bus 22, and the B interface 28 is coupled to thesecond bus 24.

In an exemplary embodiment, the processors 12, 14, 16, 18 are Power PCprocessors from Motorola Corporation of Schaumberg, Ill. The processors12, 14, 16, 18 may alternately be Alpha Processors from the DigitalEquipment Corporation of Maynard, Mass. or any other microprocessorcapable of being used in a multi-processor computer system. The firstprocessor 12, second processor 14, and fourth processor 18 each has anintegrated cache 30, 32, and 34, respectively. An integrated cache 30,32, 34 is a group of memory cells that are integrated into the samecircuit or chip as the processor 12, 14, and 18. The third processor 16has an off chip cache 36. The off chip cache 36 is integrated in aseparate circuit and is coupled to the third processor 16 by a line 38.Each cache 30, 32, 34, 36 holds data for its processor 12, 14, 16, 18.Each processor 12, 14, 16, 18 can generally access data in its cache 30,32, 34, 36 faster than it can access data in the memory 20. Furthermore,by accessing data in its cache 30, 32, 34, 36, a processor 12, 14, 16,18 does not utilize the bus 22, 24. Thus, leaving the bus 22, 24 freefor use by other devices.

The memory 20 comprises random access memory (“RAM”). The memory 20holds data and program instruction steps for the processors 12, 14, 16,18. The memory 20 will be described in greater detail with reference toFIGS. 2, 3, 4, and 5.

The A interface 26 and B interface 28 are conventional interfaces suchas IEEE Std 1596 Scalable Coherent Interfaces. The A interface 26 and Binterface 28 do not transmit memory access commands for which they arenot in the transfer path. For example, the A interface 26 and Binterface 28 would transfer memory access commands from the thirdprocessor 16 or the fourth processor 18 to the memory 20 since the pathbetween processors 16 and 18 and memory 20 is through the interfaces 26,28. The interfaces 26, 28, however, would not transmit memory accesscommands from the first processor 12 or second processor 14 since theinterfaces 26, 28 are not in the path between these processors 12, 14and the memory 20. Thus, the third processor 16 and fourth processor 18cannot eavesdrop on accesses of the memory 20 by the first processor 12or the second processor 14.

Referring now to FIG. 3, a block diagram of a first embodiment of thememory 20 constructed in accordance with the present invention is shown.The memory 20, shown in FIG. 3, comprises a data storage 72 and a memorycontroller 45. The data storage 72 comprises a plurality of memorylines. As before, each memory line 74, 76, 78 has an address. A memoryline 74 has address 0; a memory line 76 has address 1; and a memory line78 has address N−2. N is the number of memory lines in data storage 72.Each memory line 74, 76, 78 may hold data or check and tag codes. Tagscodes are contained in a tag field of a first word of each memory line74, 76, 78, and check codes are held in a check field of the first wordof each memory line 74, 76, 78. When the data of a memory line is owned(cached and possibly modified), the check field contains a GONE codevalue and the tag field holds a tag field code. The tag field code is anencoded identifier of the owning processor 12, 14, 16, 18. Memory line74 has a check field 73 and tag field 80. Similarly, memory lines 76 and78 have check fields 75 and 77, respectively as well as tag fields 82and 84, respectively. This first embodiment advantageously uses anyportion of data storage 72 for the t bit storage 86. The t bit storage86 comprises a plurality of t bit fields. Each t bit field of the t bitstorage 86 is assigned to a memory line 74, 76, or 78. For example, afirst t bit field 88 is assigned to memory line 74, a second t bit field89 is assigned to memory line 76, and a t bit field 90 is assigned tomemory line 78. A t bit field 88, 89, 90 is preferably 1 bit wide, andholds a T bit that confirms whether a memory line 74, 76, 78 holds dataor a tag.

The memory controller 45 controls the operation of the first embodimentof the memory 20 and is coupled to the data storage 72 by a line 47. Thememory controller 45 contains combinational logic circuits and datastorage device. If the memory controller 45 receives a ReadOwned signalfor the first memory line 74, the memory controller 45 first asserts asignal on the line 47 for the data storage 72 to transfer the contentsof check field 73 to the memory controller 45. If the check fieldcontains a GONE code, the memory controller 45 signals the data storageto transfer the T bit, held in t bit field 88, to the memory controller45. For example, if the check field 73 holds a GONE code and the T bitis a 1, then the data is owned; otherwise the data is unowned. If thedata is owned, the memory controller 45 outputs the code contained inthe tag field 80, onto the bus 22 along with a signal that the data isowned. If the data is not owned, the memory controller 45 outputs thecontents of the first memory line 74 onto the bus 22.

This first embodiment of the present invention eliminates the need for aseparate tag memory 42 (shown in FIG. 1) and the accompanying problemsof controller design. Although unowned data can be quickly returned andspecial tag storage is not required, two operations must still beexecuted whenever a memory line 74, 76, 78 is accessed. In this firstembodiment, the t bit storage 86 is much smaller than the tag storage42.

Referring now to FIG. 4, a second embodiment of the memory 20,constructed according to the present invention, is shown. The memory 20comprises a data storage 92 and a memory controller 94. The memorycontroller 94 is coupled to the bus 22 to receive data, address, andcontrol signals and is coupled to the data storage 92 by a first line 96for address signals, a second line 98 for control signals, and a thirdline 100 for data signals. Alternately, the memory controller 94 may becoupled to the data storage 92 by a single line. In this alternateembodiment, the single line would be used sequentially for data,address, and control signals. The memory controller 94 interpretsincoming signals, determines if data contained in the data storage 92 isfresh or is owned by another processor 12, 14, 16, or 18, and generatesand outputs data, address, and control signals on the bus 22.

The data storage 92 comprises a plurality of memory lines. Each memoryline has an address. Memory line 102 has address 0; memory line 104 hasaddress 1; and memory line 108 has address N−2. N is the number ofmemory lines in the data storage 92. Each memory line 102, 104, 106comprises one or more words, all memory lines 102, 104, 106, however,have the same number of words. Whenever an address is accessed, allwords of the memory line 102, 104, 106 at the address are accessed. Forexample, if the first memory line 102 is being read, all words of thememory line 102 are output by the memory 20. While the words may haveany number bits, currently and preferably each word comprises 64 bits. Aportion of the data storage 92 is used for storing D bits. FIG. 4 showsa final portion 108 of the data storage 92 being used for holding Dbits. Any portion of the data storage 92 may be dedicated to contain Dbits. Each D bit is one bit in length and is contained in a d bit field.The d bit fields are arranged according to the memory lines 102, 104,106 to which they are assigned. For example, a d bit field 110 isassigned to memory line 102; a d bit field 120 is assigned to memoryline 104; and a d bit field is assigned to memory line 106. Each memoryline between memory line 104 and memory line 106 also has an assigned dbit field. The D bits will be explained in greater detail below.

According to the present invention, a first word of each memory line has3 fields. As can be seen with reference to the first memory line 102 ofFIG. 4, the first word has a check field 114, a g bit field 116, and atag field 118. The check field 114, g bit field 116, and tag field 118are used in two different ways. First, if the first memory line 102 isnot owned, then the check field 114, g bit field, and tag field 118 ofthe first word are used to contain data. Second, if the memory line 102is owned, the first word is used to contain the tag. The g bit field 116is at least one bit in length, and the bits of the check field 114, gbit field 116, and tag field 116 total 64 in the exemplary embodimentthat will be described. In the exemplary embodiment, the check field 114is 32 bits in length, and the tag field 118 is 31 bits in length. Inother applications, the lengths may be different. When owned, the checkfield 114 contains a GONE code that indicates that the data held inmemory line 102 is owned by a processor 12, 14, 16, 18. The GONE codevalue is preferably generated by the memory controller 94. If the GONEcode is not contained in the check field 114, then the memory line 102contains unowned data, and the contents of the check field 114, g bitfield 116, and tag field 118 are a part of the data. There is a rarecase where the check field 114 holds unowned data that happens by chanceto match the GONE code. If the data is owned by a processor 12, 14, 16,18, then the tag field 118 holds a coded identification of the owningprocessor 12, 14, 16, 18, a tag. The g bit field 116 is required for therare situations where unowned data contained in the first memory line102 matches the GONE code that is normally contained in the check field114 and used to indicate that the data is owned by a processor 12, 14,16, 18. When data is owned by a processor 12, 14, 16, 18, the checkfield 114 holds the GONE code indicating ownership, and the g bit field116 contains a 1. If the data is not owned but the data held in thecheck field 114 matches the GONE code used to indicate that the data isowned, the g bit field 116 contains a 0. In this case, the g bit field114 contains a 0 regardless of whether the actual data is a 1 or a 0,and the d bit field 110 is set to hold the actual data value of the Gbit. Thus for most memory accesses, the present invention requires onlyone read function. Only when the data in the check field 114 matches theGONE code used to indicate ownership and the g bit field 116 holds a 0,must there be a second read function to determine the true data value ofthe G bit. In this case the true data value of the G bit is obtainedfrom the assigned D bit.

The GONE code contained in the check field 114 and used to indicate thatthe data is owned may be any code value. Preferably, the GONE code isthe result of a hashing function where the input to the hashing functionis the address of the first memory line 102. For example, when using a32-bit address, a 32-bit hashing function may be an exclusive-or of theaddress and the bit-reversed version of the address. Alternately, whenusing a 64 bit address, a 32-bit hashing function may be an exclusive-orof the even bits and the bit-reversed odd bits. There are many otherhashing functions that may be employed with the present invention, andthose skilled in the art will recognize these functions.

The present invention advantageously eliminates the need to eavesdrop onmemory accesses by other processors 12, 14, 16, 18. Whenever a processor12, 14, 16, 18 accesses a memory address, the processor 12, 14, 16, 18either receives valid data or receives the identity of the processor 12,14, 16, 18 that owns the valid data. The present invention does thiswithout having to modify the size or shape of the memory 20 or bus 22.The present invention is particularly advantageous because the uniquefield system of check fields. G bit fields, and tag fields greatlyimproves the performance of the memory controller. While the prior artrequired two memory controller accesses of the data storage to providethe data and even more for outputting the tag, the present invention isable to provide the data or the tag in a majority of instances with onlya single access of the data storage. Furthermore, the second embodimentshown in FIG. 4 is an improvement over the first embodiment shown inFIG. 3. The first embodiment requires a second access of the datastorage 72 whenever the data held in the check field 73, 75, 77 matchesthe GONE code. By contrast, the second embodiment requires a secondaccess in the rare instances when the data is unowned and matches theGONE code; that is the data held happens by chance to match the GONEcode for the memory line 102, 104, 106. This eliminates some of thesecond accesses required by the first embodiment.

Referring now to FIG. 5, a block diagram of the second embodiment of thememory 20, with the memory controller 94 in detail, is shown. The memorycontroller 94 comprises a memory sequencer 122, a data buffer 124, andan address buffer 126. The memory controller 94 may include otherelements of conventional memories such as systems for refreshing thememory; these conventional elements may alternatively be in anotherstructure. The data buffer 124 is a conventional buffer for receivingdigital data. The data buffer 124 has a first input/output and a secondinput/output and a control input. The first input/output and the secondinput/output are bi-directional, that is they may either receive ortransmit digital data. The first input/output is coupled to the data busof the bus 22 to receive and transmit data signals. The secondinput/output of the data buffer 124 is coupled to the data storage 92 bythe line 100. Similarly, the address buffer 126 is a conventional bufferfor storing addresses. The address buffer 126 has an input, which iscoupled to the address bus of the bus 22, for receiving addresses, acontrol input, and an output. The output of the address buffer 126 iscoupled to the data storage 92 by line 96.

The memory sequencer 122 is a state machine that receives signals andgenerates signals for controlling accesses to the data storage 92. Thememory sequencer 122 comprises combinational logic and data storagedevices to implement its functions. Those skilled in the art willrealize how to construct a memory sequencer 122 from the inputs,outputs, and states that are described below. The memory sequencer 122has a first input/output, coupled to the address buffer 126 and to thedata storage 92 by line 96, for receiving and transmitting addresses. Asecond input/output is coupled to the data buffer 124 and to the datastorage 92 by line 100. The memory sequencer 122 receives and outputsdata signals through the second input/output. The memory sequencer 122has a first output for transmitting control signals to the data storage92. The first output is coupled to the data storage by line 98. Thememory sequencer 122 transmits data control signals to the data buffer124 through a second output. The second output is coupled to the databuffer 124 by a line 128. A third output of the memory sequencer 122transmits address buffer control signals and is coupled to the addressbuffer 126 by a line 130. The memory sequencer 122 outputs signalsindicating the identity of a processor 12, 14, 16, 18 that owns datathat another processor 12, 14, 16, 18 is attempting to access onto thecontrol bus of the bus 22 through a fourth output. The fourth output iscoupled to the control bus of the bus 22 and is labeled “Last Owner.”Often when a processor 12, 14, 16, 18 attempts to access memory line102, that processor 12, 14, 16, 18 becomes the new owning processor 12,14, 16, 18 that is identified in the tag field 118. If another processor12, 14, 16, 18 already owns the data, the accessing processor 12, 14,16, 18 will request the data from the prior owner. Thus, the accessingprocessor 12, 14, 16, 18 becomes the new owner. For this reason, thefourth output of the memory sequencer 122 is labeled “Last Owner.” Thememory sequencer 122 has a fifth output that is coupled to the controlbus of the bus 22. The memory sequencer 122 outputs a Status signal,which indicates the success of the memory access, through the fifthoutput. If another processor 12, 14, 16, 18 owns the data, the memorysequencer 122 generates and outputs, through the fifth output, a DIFFStatus signal. If the data is unowned, the memory sequencer 122generates and outputs, through the fifth output, a NONE Status signal.The memory sequencer 122 generates and outputs a SAME Status signal incertain situations. The memory sequencer 122 would generate the SAMEStatus signal if the accessing processor 12, 14, 16, 18 is the processoridentified in the tag field 118 as the owning processor 12, 14, 16, 18.

The memory sequencer 122 has a first input, which is coupled to thecontrol bus of the bus 22, through which the memory sequencer 122receives the identity of the processor 12, 14, 16, 18 which isattempting a memory access, and the memory sequencer 122 has a secondinput, also coupled to the control bus of the bus 22, through which thememory sequencer 122 receives the command of the processor 12, 14, 16,18. The first input is labeled CacheId, and the second input is labeledCMD.

The two basic commands are ReadOwned and WriteReturn. The ReadOwnedcommand is used when the accessing processor 12, 14, 16, 18 is to becomethe owning processor 12, 14, 16, 18 on the completion of the command.The WriteReturn command is used when the accessing processor 12, 14, 16,18 is to write data that becomes unowned. If a processor 12, 14, 16, 18attempts a ReadOwned command on data that another processor 12, 14, 16,18 owns, the accessing processor 12, 14, 16, 18 becomes the owningprocessor 12, 14, 16, 18 and DIFF Status signal is generated. Theaccessing processor 12, 14, 16, 18 then requests the data from the lastowning processor 12, 14, 16, 18. If a processor 12, 14, 16, 18 attemptsa ReadOwned on unowned data, a NONE Status signal is generated, the datais returned to the accessing processor 12, 14, 16, 18, and the accessingprocessor 12, 14, 16, 18 becomes the owner of the data. If a processor12, 14, 16, 18 attempts a ReadOwned command on data it owns, a SAMEStatus signal results and no data is returned. This is usually an errorcondition. When a WriteReturn command is issued on data that is owned bythe accessing processor 12, 14, 16, 18, the data, from the accessingprocessor 12, 14, 16, 18, is written at the memory location, a SAMEStatus signal is generated, and the data becomes unowned. When aWriteReturn command is issued on data owned by a processor 12, 14, 16,18 other than the accessing processor 12, 14, 16, 18, a DIFF Statussignal is generated, and neither ownership nor the data held in thememory 20 is modified. Finally, when a WriteReturn command is issued onunowned data, a NONE Status signal is generated, and the data is notmodified. This last situation is usually an error situation. There aretwo additional commands that are closely related to the ReadOwned andWriteReturn commands. These commands are ReadFresh and WriteCheck. TheReadFresh command is used when unowned data is to be read and is toremain unowned when the command is completed. The ReadFresh command issimilar to the ReadOwned command, but when the ReadFresh command isexecuted on unowned data, the data remains unowned. The WriteCheckcommand is used to update unowned data and that data is to remainunowned. If the WriteCheck command is issued on data owned by aprocessor 12, 14, 16, 18 other than the accessing processor, a DIFFStatus signal is generated, the data is modified, and ownership changesto the accessing processor 12, 14, 16, 18. If a WriteCheck command isissued on unowned data, the data in the memory line is modified, a NONEStatus signal is generated, and the data in the memory line remainsunowned. Finally, if the WriteCheck command is issued on data owned bythe accessing processor 12, 14, 16, 18, a SAME Status signal isgenerated; this is usually an error situation. There are other possiblecommands. From the commands described here, those skilled in the artwill recognized these commands.

Referring now to FIG. 6, a state diagram for an exemplary embodiment ofthe memory sequencer 122 is shown. FIG. 6 shows the significant statesof the memory sequencer 122; other states may be necessary to implementfully the memory sequencer 122. These additional states will beunderstood by those skilled in the art. FIG. 6 shows the significantstates for the ReadOwned and WriteReturn commands. Those skilled in theart will recognize the states necessary for other commands. The memorysequencer 122 receives command signals through its CMD input, addressdata through the input to the address buffer 126, and a CacheId signalthrough its CacheId input. The CacheId signal identifies the accessingprocessor 12, 14, 16, 18. When the memory sequencer 122 receives aReadOwned, WriteReturn, or other appropriate command signal, the memorysequencer 122 generates a signal and asserts the signal on line 130 forthe address buffer 126 to capture the address and to transfer theaddress to the memory sequencer 122. The address buffer 126 transfersthe address by asserting a signal on line 96, which is coupled to theaddress input/output of the memory sequencer 122. The memory sequencer122 then analyzes the address to determine if the address is for alocation within the data storage 92. As shown in FIG. 2, the computersystem 10 has only one memory 20. Computer systems may, however, havemultiple memories. Where a computer system has multiple memories, thememory sequencer 122 must determine if the address is within its datastorage 92. If the address is not for an address within its data storage92, the memory sequencer 122 remains in state I.

If the address is for a location within the data storage 92, the memorysequencer 122 enters state II. For this explanation, it will be assumedthat the received address is 0, and the memory line to be accessed isthe first memory line 102. Those skilled in the art will realize how thedescription applies to all memory lines of the data storage 92. In stateII, the memory sequencer 122 generates the GONE code for the address 0.As described above with reference to FIG. 5, the memory sequencer 122preferably uses a hashing function to generate the GONE code for theaddress. The memory sequencer 122 then generates a signal instructingthe data storage 92 to output the first word of the first memory line102 at the address to the memory sequencer 122. The memory sequencer 122transmits the signal to this data storage 92 on line 98, and inresponse, the data storage 92 transmits the first word to the memorysequencer 122 on line 100. The memory sequencer 122 outputs the datacontained in the tag field 118 of the first word, through its Last Owneroutput, onto the control bus of the bus 22. Note that the memorysequencer 122 has not yet determined if memory line 102 is owned by aprocessor 12, 14, 16, 18. If the first memory line 102 is not owned, thetag that has been output is meaningless and will be ignored. If thefirst memory line 102 is owned, the data in the tag field 118 identifiesthe owning processor and will be used by the accessing processor 12, 14,16, 18. Once the memory sequencer 122 has output the data from the tagfield 118 through the Last Owner output, it compares the data in thecheck field 114 to the GONE code that it just generated. The memorysequencer 122 then transitions out of state II.

If the memory sequencer 122 received a ReadOwned command at its CMDinput and the GONE code does not match the data contained in the checkfield 114, the memory sequencer 122 transitions from state II to stateIII. In this case, the first memory line 102 is not owned by anyprocessor 12, 14, 15, 18, since the GONE code is not equal to the dataheld in the check field 114. In state III, the memory sequencer 122asserts a signal on line 98 instructing the data storage 92 to outputthe contents of the first memory line 102 onto line 100. The memorysequencer 12 then asserts a signal on line 128 for the data buffer 124to receive the data and to output the data onto the data bus of the bus22. This is done for each word until the entire contents of memory line102 have been transferred to the bus 22. The first memory line 102 isnow owned by the accessing processor 12, 14, 16, 18. The memorysequencer 122 signals the data storage 92 to store the GONE code, whichthe memory sequencer 122 determined in state II, in the check field 114,to set the G bit in the g bit field 116 to 1, and to store the identityof the accessing processor 12, 14, 16, 18 in the tag field 118. Thememory sequencer 122 received the identity of the accessing processor12, 14, 16, 18 through its CacheId input. Finally, the memory sequencer122 generates a NONE Status signal and asserts this signal onto thecontrol bus through the Status output. The memory sequencer 122 thenleaves state III and returns to state I.

If in state II, the memory sequencer 122 determines that the GONE codematches the data held in the check field 114 and the memory sequencer122 received a ReadOwned signal, the memory sequencer 122 enters stateIV. The first memory line 102 may be owned by a processor 12, 14, 16,18; it is also possible that the data contained in check field 114simply matches the GONE code. In state IV, the memory sequencer 122 getsthe G bit from the g bit field 116. The memory sequencer 122 has alreadyobtained the first word from the data storage 92 in state II. If the Gbit is 0, the first memory line 102 is unowned and the memory sequencer122 proceeds to state V. In state V, the memory sequencer 122 signalsthe data storage 92 to transfer the value of the D bit for the firstmemory line 102, which is held in the d bit field 110, to the memorysequencer 122. The memory sequencer 122 then sets the value contained inthe g bit field 116 equal to the value of the D bit and proceeds tostate III. This is the very rare occurrence where the present inventionmust make two reads to accomplished the memory access. This only occurswhen the data held in a memory line is unowned, and the data held in thecheck field happens by chance to match the GONE code.

If in state IV, the G bit, contained in the g bit field 116, is equal to1, the memory sequencer 122 checks the tag held in the tag field 118. Ifthe tag matches the CacheId received at the CacheId input, the memorysequencer 122 moves to state VI. In this case, the first memory line 102is owned by the accessing processor 12, 14, 16, 18. The data held in thefirst memory line 102 may not be read since it is owned. In state VI,the memory sequencer 122 generates a SAME Status signal and asserts thesignal on the control bus through the Status output. A SAME Statussignal indicates that a memory line is owned by the accessing processor12, 14, 16, 18 and usually indicates an error condition. The memorysequencer 122 then returns to state I.

If in state IV the G bit is 1 and the tag does not match the CacheIdreceived at the CacheId input, the memory sequencer 122 enters stateVII. As in State VI, the data in the first memory line 104 of the datastorage 92 is not valid data. The memory sequencer 122 generates andoutputs a DIFF Status signal. The DIFF Status signal indicates that thefirst memory line 104 is owned. The memory sequencer 122 already outputthe identity of the owning processor 12, 14, 16, 18 when it output thecontents of the tag field 118 in state I. The accessing processor 12,14, 16, 18 will receive the DIFF Status signal along with the contentsof the tag field 118, and the accessing processor 12, 14, 16, 18 willthen be able to obtain the valid data by requesting the data from theowning processor 12, 14, 16, 18. The memory sequencer 122 then signalsthe data storage 92 to store an identifier for the accessing processor12, 14, 16, 18 in the tag field 118. The accessing processor 12, 14, 16,18 now becomes the owner of the first memory line 102. The memorysequencer 122 then returns to state I.

In state II, if the memory sequencer 122 received a WriteReturn signalin state I, the memory sequencer 122 moves to state VIII. With theWriteReturn command, only an owning processor 12, 14, 16, 18 may writeto a memory line. In state VIII, the memory sequencer 122 compares theGONE code determined in state II from the address to the code containedin the check field 114 and compares the CacheId signal received from thecontrol bus to the tag held in the tag field 118. The memory sequencer122 also determines if the G bit contained in the g bit field 116 isa 1. If the first memory line 102 is owned by another processor 12, 14,16, 18, then the memory sequencer 122 moves to state IX. The firstmemory line 102 is owned by another processor 12, 14, 16, 18 if the codeheld in the check field 114 matches the GONE code that the memorysequencer 122 generated from the address in state II, if the G bitcontained in the g bit field 114 is 1, and if the tag held in the tagfield 118 does not match the CacheId signal received from the controlbus. If any one of these three conditions is not met, then the firstmemory line 102 is not owned by another processor 12, 14, 16, 18 and thememory sequencer 122 does not enter state IX. In state IX, the memorysequencer 122 generates a DIFF Status signal and asserts this signal onthe control bus of the bus 22. The memory sequencer 122 then returns tostate I.

If, in state VIII, the first memory line 102 is unowned, the memorysequencer 122 moves to state X. An accessing processor may only write toa memory line owned by itself. The first memory line 102 is unowned ifone of two conditions is met. The first condition is that the code, heldin the check field 114, does not match the GONE code generated in stateII. The second condition is that the code, held in the check field 114,matches the GONE code generated in state II, but the G Bit, held in theg bit field 116, is a 0. In state X, the memory sequencer 122 generatesa NONE Status signal. As was explained above, this is usually an errorcondition. The memory sequencer 122 then returns to state I.

If, in state VIII, the first memory line 102 is owned by the accessingprocessor 12, 14, 16, 18, the memory sequencer 122 enters state XI. Thefirst memory line 102 is owned by the accessing processor 12, 14, 16, 18if three conditions are met. The first condition is the code held in thecheck field 114 matches the GONE code generated by the memory sequencer122 from the address in state II. The second condition is the G bit,held in the g bit field 116, is a 1. The third condition is the CacheIdsignal, received from the control bus, matches the tag held in the tagfield 118. If these three conditions are met, the memory sequencer 122proceeds to state XI.

In state XI, the memory sequencer 122 generates a signal and asserts thesignal on line 128 for the data buffer 124 to transfer the first word ofthe data to be written in the first memory line 102 to the memorysequencer 122. The memory sequencer 122 then compares the GONE codegenerated in state II to the data received from the data buffer 124.Note that in state VIII, the memory sequencer 122 compared the GONE codeto the data contained in the check field 114. In state XI, however, thememory sequencer 122 is comparing the GONE code to the first 32 bits ofthe first word of the data that is entering the memory 20. The memorysequencer 122 is not comparing the GONE code to the data already held inthe memory 20. When a processor 12, 14, 16, 18 writes data to the memory20 the data becomes unowned. The memory sequencer 122 must, however,determine if the data, by chance, matches the GONE code. If the first 32bits of the first word match the GONE code, the memory sequencer 122moves to state XII. In state XII, the memory sequencer 122 sets the Dbit to the value of the G bit of the first word and records this valuein the d bit field 110. The memory sequencer 122 then assigns to the Gbit the value of 0.

From state XII or, if the data did not match the GONE code, from stateXI, the memory sequencer 122 enters state XIII. In state XIII, thememory sequencer 122 first generates a signal instructing the datastorage 92 to store the incoming data in the first memory line 102. Thefirst word is transmitted from the memory sequencer 122, the remainderis transmitted from the data buffer 124. The memory sequencer 122 thengenerates a SAME Status Signal. The SAME Status signal indicates to theaccessing processor 12, 14, 16, 18 that the WriteReturn was successful.The memory sequencer 122 then returns to state I.

Referring now to FIGS. 7A, 7B, and 7C, flow charts of a method foraccessing a memory utilizing the present invention are shown. The methodbegins in step 200 where a memory sequencer 122 receives address,control, and data signals. The memory sequencer 122 receives an addresssignal, a command signal, and a CacheId signal that identifies theaccessing processor 12, 14, 16, 18. In step 202, the memory sequencer122 determines if the address is within its associated data storage 92.If the address is not within the data storage 92, the method returns tostep 200 to await another address. If the address is within the datastorage 92, the method moves to step 204.

In step 204, the memory sequencer 122 determines a GONE code from theaddress. The memory sequencer 122 may use any method for generating theGONE code. The memory sequencer 122 preferably uses a hashing functionto generate the GONE code. For example, if a 32 bit address is used, thememory sequencer 122 may use an exclusive-or of the address and thebit-reversed version of the address. Alternately, if a 64 bit address isused, the memory sequencer 122 may use an exclusive-or of the even bitsof the address and the bit-reversed version of the odd bits. There aremany other hashing functions that may be used; those skilled in the artwill recognize these functions. Also in step 204, the memory sequencer122 signals for and receives the first word of data contained in theaddressed memory line. In this description it will be assumed that theaddress was 0 and the first memory line 102 is to be accessed. Thoseskilled in the art will recognize how the method applies to all memorylines of the data storage 92.

In step 206, the memory sequencer 122 outputs, through its Last Owneroutput, onto the control bus of the bus 22, data held in a tag field 118of the first memory line 102. If the first memory line 102 is owned,then the tag identifies the owning processor 12, 14, 16, 18 to theaccessing processor 12, 14, 16, 18. If the first memory line 102 is notowned, then the tag will be ignored. In step 208, the memory sequencer122 determines if the control signal received through its CMD input is aReadOwned command. The memory sequencer 122 ignores command signals onthe bus 22 that do not affect the memory 20. For this description itwill be assumed that there are only two memory operations, ReadOwned andWriteReturn. Those skilled in the art will realize how the method may bemodified for other memory operations such s ReadFresh, WriteCheck, andothers. If the command is a ReadOwned command, the method moves to step210 where the memory sequencer 122 compares the GONE code, determined instep 204, to the data contained in the check field 114. If the GONE codedoes not match the data contained in the check field 114, the memorysequencer 122, in step 212, signals the data storage 92 and data buffer124 to output the contents of the first memory line 102 onto the databus of the bus 22. The memory sequencer 122 also generates and outputs,through its Status output, onto the control bus a NONE Status signal. Instep 214, the memory sequencer 122 signals the data storage 92 to storethe GONE code, generated in step 204, in the check field 114, a 1 in theg bit field 116, and the CacheId, received from the control bus throughthe CacheId input, in the tag field 118. This identifies the firstmemory line 102 as owned by the accessing processor 12, 14, 16, 18 whichwas identified by the input through the CacheId input. The method thenends.

If in step 210 the GONE code did not does match the data held in thecheck field 112, the method continues in step 236 of FIG. 7B. In step236, the memory sequencer 122 determines if the G bit is equal to 0. TheG bit is held in the g bit field 116. If the G bit is equal to 0, themethod continues in step 238. This is the rare situation where the datacontained in memory line 102 is not owned, but the data held in thecheck field 114, by chance, matches the GONE code generated from theaddress for memory line 102. This is the situation where a second readfunction must be executed. In step 238, the memory sequencer 122 signalsthe data storage 92 to read the D bit contained in the d bit field 110and to provide the D bit to the memory sequencer 122. In step 240, thememory sequencer 122 sets the G bit equal to the D bit. Since the datacontained in the memory line 102 is not owned and the data contained inthe check field 112 happened to match the GONE code, the G bit wasforced to 0. This 0 value for the G bit indicates that the data is notowned. The D bit is the actual data value of the bit occupied by the Gbit. By setting the G bit equal to the D bit before outputting the data,the memory sequencer 122 restores the true value of the bit occupied bythe G bit. Next, in step 242, the memory sequencer 122 transfers thefirst word of the first memory line 102, with the restored D bit, to thedata buffer 124 and signals the data buffer 124 and data storage 92 tooutput the contents of the first memory line 102 onto the data bus ofthe bus 22. The memory sequencer 122 also generates and outputs a NONEStatus signal.

The memory sequencer 122 then, in step 246, signals the data storage 122to store the GONE code, generated in step 204, in the check field 114, a1 in the g bit field 116, and the CacheId, received from the control busthrough the CacheId input, in the tag field 118. This identifies thefirst memory line 102 as owned by the accessing processor 12, 14, 16, 18which was identified by the input through the CacheId input. The methodthen ends.

If in step 236 the G bit was not equal to 0, then the first memory line102 is owned by a processor 12, 14, 16, 18 and the data storage 92 doesnot have valid data. The accessing processor 12, 14, 16, 18 must requestthe data from the owning processor 12, 14, 16, 18. In step 244, thememory sequencer 122 determines if the CacheId signal matches the tagheld in the tag field 118. If the CacheId signal matches the tag, themethod continues in step 248. In step 250, the memory sequencer 122generates and outputs a SAME Status signal. This is usually an errorcondition, and the method ends. If in step 244 the tag does not matchthe CacheId input, the memory sequencer 122 generates, in step 248, aDIFF Status signal and outputs this signal onto the control bus of thebus 22. The accessing processor 12, 14, 16, 18 will receive this signaland, having already received the tag output in step 206, will requestthe data from the owning processor 12, 14, 16, 18. The memory sequencer122 assumes that the accessing processor 12, 14, 16, 18 will receive thedata from the owning processor 12, 14, 16, 18. Therefore, the methodproceeds to step 246 where the memory sequencer 122 identifies the firstmemory line 102 as owned by the accessing processor 12, 14, 16, 18. Themethod then ends.

If in step 208 the command is not a ReadOwned command, the command mustbe a WriteReturn command. In step 216 the memory sequencer 122determines if the data contained in the check field 114 matches the GONEcode and if the G bit, held in the g bit field 116, is 1. If eithercondition is false, then the first memory line 102 is not owned. This isusually an error condition. In step 218, the memory sequencer 122generates and outputs a NONE Status signal. After step 218, the methodends.

If both conditions of step 216 are true, the first memory line 102 isowned. In step 220, the memory sequencer 122 determines if the datacontained in the tag field 118 matches the CacheId received through theCacheId input. If the tag matches the CacheId, then the accessingprocessor 12, 14, 16, 18 is the owner. If there is no match, the memorysequencer 122 generates a DIFF Status signal in step 222, outputs theDIFF Status signal, and the method ends.

If the accessing processor 12, 14, 16, 18 is the owner, then the methodcontinues in step 224 of FIG. 7C. In step 224, the memory sequencer 122determines if the first bits of the incoming data match the GONE code.Note that the memory sequencer 122 is comparing the incoming data to theGONE code. In step 216, the memory sequencer 122 compared the dataalready contained in the first memory line 102 to the GONE code. Ifthere is no match in step 224, the memory sequencer 122 signals, in step226, the data buffer 124 and data storage 92 to store the data in thefirst memory line 102. The memory sequencer 122 generates and outputs aSAME Status signal, and the method ends. If in step 224 there is amatch, the memory sequencer 122 sets the D bit equal to the G bit instep 228. The memory sequencer 122 then in step 230 signals the datastorage to store the D bit in the d bit field 110. In step 232, thememory sequencer 122 sets the G bit equal to 0, and in step 234 thememory sequencer 122 signals the data buffer 124 and data storage 92 tostore the data in the first memory line 102. The data storage 92 storesthe data with the G bit set to 0. The memory sequencer 122 thengenerates and outputs a SAME Status signal, and the method ends.

While the present invention has been described with reference to certainpreferred embodiments, those skilled in the art will recognize thatvarious modifications may be provided. For example, the presentinvention is described for performing certain memory operations, thepresent invention may be used to perform any operation. The g bit fieldneed not comprise only one bit. The g bit field may comprise more thanone bit and may contain data in addition to data indicating that,despite matching check field data and GONE code values, the memory lineis unowned and contains data. These and other variations upon andmodifications to the preferred embodiments are provided for by thepresent invention, which is limited only by the following claims.

What is claimed is:
 1. A memory system for a computer system having aplurality of processors, the memory system comprising: a data storagedevice having address and data inputs, outputs, a command input, aplurality of memory lines, and a bit field portion, each memory linehaving a tag field portion for holding a processor identification codewhen not being used to hold data and having a check field portion forholding a GONE code, the bit field portion having at least one bit foreach memory line for holding a flag indicates whether the tag fieldportion of the memory line holds said processor identification code; anda memory controller having inputs and outputs coupled to communicatecommands, addresses, and data with the processors, the memory controllercoupled to the data storage device for storing and retrieving data andprocessor identification codes in the tag field portions of the memorylines, said GONE code in the check field portion of a memory line whenthe tag field portion thereof contains said processor identificationcode, and the flags in the bit field portion of the data storage device,the memory controller using information received from the processors todetermine the appropriate updating of the flags for properly indicatingwhich tag field portions contain said processor identification code;wherein the memory controller further comprises: a data buffer, havinginputs and outputs coupled to the data inputs and outputs of the datastorage device, for receiving and outputting data; an address buffer,having inputs coupled to the plurality of processors, and having inputsand outputs coupled to the address inputs of the data storage device,for receiving addresses; and a memory sequencer, having inputs andoutputs, the outputs coupled to control input of the data storagedevice, the address buffer, and the data buffer, generating signals thatinstruct the data storage device to store and retrieve said data andsaid processor identification codes for updating the bit field portionof the data storage device.
 2. The memory system of claim 1, furthercomprising a plurality of t bit fields, each t bit field being assignedto a corresponding memory line for confirming whether the tag fieldportion of said memory line holds a processor identification code. 3.The memory system of claim 1, wherein each memory line further comprisesa g bit field for confirming whether the check field portion of thememory line holds the GONE code, thereby indicating whether the tagfield portion of the memory line holds a processor identification code.4. The memory system of claim 3, wherein a g bit field is one or morebits of a memory line, and wherein the bit field portion comprises aplurality of d bit fields, with each memory line having an assigned dbit field for holding data for the portion of the memory line occupiedby the g bit field.
 5. The memory system of claim 1, wherein a memoryline has an address, and wherein the GONE code for the memory line is aresult of a hashing function applied to the address of the memory line.6. The memory system of claim 1, wherein the memory sequencer containscombinational logic.
 7. The memory system of claim 1, wherein eachmemory line of the data storage device has an unique address and theGONE code is based on the address.
 8. The memory system of claim 7,wherein the GONE code held in the check field of a memory line is aresult of a hashing function performed on the address of the memoryline.
 9. A method for reading a data storage device having memory linesaddressed by memory addresses, the method comprising the steps of:receiving a memory address for requested data and a read command from aprocessor; retrieving from the data storage device information held inthe memory line addressed by the memory address; generating a GONE codefor the memory line; comparing the GONE code to the informationretrieved; outputting the information retrieved as the requested data ifthe GONE code does not match the information retrieved; generating asignal indicating that a processor holds the requested data if the GONEcode matches the information retrieved; determining whether a G bitindicates that a processor holds requested data of the memory address,if the GONE code matches the information retrieved; retrieving a D bitif the G bit indicates that a processor does not hold the requested dataand the GONE code matches the information retrieved; and outputting theinformation retrieved as the requested data, with the D bit replacingthe G bit, if in the determining step the G bit indicated that aprocessor does not hold the requested data.
 10. The method of claim 9,further comprising the steps of: generating a signal indicating that aprocessor holds the requested data if in the determining step the G bitindicated that a processor holds the requested data; and modifying theinformation being held in the memory line addressed by the memoryaddress so that it identifies the processor that generated the readcommand.
 11. The method of claim 9, wherein the step of outputtingcomprises the steps of: outputting the information retrieved; storingthe GONE code in the memory line addressed by the memory address;storing a G bit in the memory line, the G bit indicating that aprocessor holds the requested data; and storing the identity of theprocessor which generated the read command in the memory line.
 12. Amethod for writing a data storage device having memory lines addressedby memory addresses, the method comprising the steps of: receiving aprocessor identifier, a write command, a memory address, and data from aprocessor; generating a GONE code for the memory line addressed by thememory address; comparing the GONE code to information being held in thememory line; comparing the processor identifier to the information beingheld in the memory line if the GONE code matches the information beingheld in the memory line; generating a first signal indicating that adifferent processor than the processor that generated the write commandowns a right to provide data addressed by the memory address, if theGONE code matches and the processor identifier does not match theinformation being held in the memory line, otherwise generating a secondsignal indicating that the processor that generated the write commandhas a right to write the memory line; and storing the data received inthe receiving step in the memory line unless said different processorowns a right to provide data addressed; wherein the step of storingfurther comprises the steps of: storing the data, received in thereceiving step, in the memory line addressed by the memory address;comparing the data, received in the receiving step, to the GONE code forthe memory line; recording data value of a G bit taken from the data asa D bit, if the data matches the GONE code for the memory line; andsetting the G bit to indicate that the data is not held by the processorif the data matches the GONE code for the memory line.
 13. A system forreading a data storage device having memory lines addressed by memoryaddresses, the system comprising: means for receiving a memory addressfor requested data and a read command from a processor; means forretrieving from the data storage device information held in the memoryline addressed by the memory address; means for generating a GONE codefor the memory line; means for comparing the GONE code to theinformation retrieved; means for outputting the information retrieved asthe requested data if the GONE code does not match the informationretrieved; means for generating a signal indicating that a processorholds the requested data, if the GONE code matches the informationretrieved; means for determining whether a G bit indicates that aprocessor holds requested data, if the GONE code matches the informationretrieved; means for retrieving a D bit if the G bit indicates that aprocessor does not hold the requested data; means for modifying the Gbit equal to the D bit if the G bit indicated that a processor does nothold the requested data; and means for outputting the informationretrieved as the requested data, with the modified G bit, if prior toreplacement, the G bit indicated that a processor does not hold therequested data.
 14. The system of claim 13, further comprising: meansfor generating a signal indicating that a processor holds requested dataif in the determining step the G bit indicated that a processor holdsthe data; means for generating a signal that indicates the processorthat holds the requested data; and means for modifying the informationbeing held in the memory line addressed by the memory address so that itidentifies the processor that generated the read command.
 15. The systemof claim 13, wherein the means for outputting comprises: means foroutputting the retrieved information; means for storing the GONE code inthe memory line addressed by the memory address; means for storing a Gbit in the memory line, the G bit indicating that a processor holds therequested data; and means for storing the identity of the processor thatgenerated the read command in the memory line.
 16. A system for writinga data storage device having memory lines addressed by memory addresses,the system comprising: means for receiving a processor identifier, awrite command, a memory address, and data from a processor; means forgenerating a GONE code for the memory line addressed by the memoryaddress; means for comparing the GONE code to information being held inthe memory line; means for comparing the processor identifier to theinformation being held in the memory line, if the GONE code matches theinformation being held in the memory line; means for generating a firstsignal indicating that a different processor than the processor thatgenerated the write command owns a right to provide data addressed bythe memory address if the GONE code matches and the processor identifierdoes not match the information being held in the memory line; means forgenerating a second signal indicating that the processor that generatedthe write command has a right to write the memory line if either theGONE code does not match or the processor identifier matches theinformation being held in the memory line; and means for storing thedata received in the receiving step in the memory line unless saiddifferent processor owns a right to provide data addressed by the memoryaddress; wherein the means for storing further comprises: means forstoring the data, received by the means for receiving, in the memoryline addressed by the memory address; means for comparing the data,received by the means for receiving, to the GONE code for the memoryline; means for recording data value of a G bit taken from the data as aD bit, if the data matches the GONE code for the memory line; and meansfor setting the G bit to indicate that the data, received by the meansfor receiving, is not held by the processor if the data matches the GONEcode for the memory line.
 17. A memory system for a computer systemhaving a plurality of processors, the memory system comprising: a datastorage device comprising a plurality of memory lines, each memory linehaving a tag field and a check field, the data storage device furtherincluding a bit field; and a memory controller coupled to said pluralityof processors for communicating read commands, write commands, and datatherewith, the memory controller further coupled to the data storagedevice for reading and writing data in the memory lines thereof,including in the check and tag fields thereof, in response to saidcommands, and for reading and writing GONE codes and processoridentifiers in the check and tag fields respectively when said fieldsare not holding data from the processors; wherein data from plurality ofprocessors can match the GONE codes of the memory lines, and the memorycontroller writes in the bit field an indication of authenticity of eachGONE code written in the check field, and wherein in response toreceiving a command to read the first memory line from first processor,the memory controller further supplies the contents thereof to saidfirst processor in response to the contents of the check field matchingthe GONE code thereof and the contents of the bit field notauthenticating said matching of the GONE code thereof.
 18. The memorysystem of claim 17, wherein: in response to receiving a command to reada memory line from a processor, the controller reads the memory line,supplies the contents thereof to the processor in response to thecontents of the check field thereof not matching the GONE code thereof,writes the processor identifier of the processor to the tag fieldthereof, and writes the GONE code thereof in the check field thereof.19. The memory system of claim 17, wherein: in response to receiving acommand to write data in a memory line from a processor, the controllerreads the check and tag fields thereof, writes the data therein inresponse to the contents of the check field thereof not matching theGONE code thereof, and writes said data therein in response to thecontents of the tag field thereof matching the processor identifier ofthe processor.
 20. A method for writing a data storage device havingmemory lines addressed by memory addresses, the method comprising thesteps of: receiving a processor identifier, a write command, a memoryaddress, and data from a processor; generating a GONE code for thememory line addressed by the memory address; comparing the GONE code toinformation being held in said memory line; comparing the processoridentifier to said information; generating a signal in response toeither the GONE code not matching said information or the processoridentifier matching said information; and storing the data received inthe receiving step in the memory line in response to said signal;wherein the step of storing comprises the steps of: storing the data,received in the receiving step, in the memory line addressed by thememory address; comparing the data, received in the receiving step, tothe GONE code for the memory line; recording data value of a G bit takenfrom the data as a D bit, if the data matches the GONE code for thememory line; and setting the G bit to indicate that the data is not heldby a processor if the data matches the GONE code for the memory line.21. A system for writing a data storage device having memory linesaddressed by memory addresses, the system comprising: means forreceiving a processor identifier, a write command, a memory address, anddata from a processor; means for generating a GONE code for the memoryline addressed by the memory address; means for comparing said GONE codeto information being held in the memory line; means for comparing theprocessor identifier to said information; means for generating a signalin response to either the GONE code not matching said information or theprocessor identifier matching said information; and means for storingthe data received in the receiving step in the memory line in responseto said signal; wherein the means for storing comprises: means forstoring the data, received by the means for receiving, in the memoryline addressed by the memory address; means for comparing the data,received by the means for receiving, to the GONE code for the memoryline; means for recording data value of a G bit taken from the data as aD bit, if the data matches the GONE code for the memory line; and meansfor setting the G bit to indicate that the data, received by the meansfor receiving, is not held by said processor if the data matches theGONE code for the memory line.
 22. A method of managing memory access toa data storage in a multi-processor system including a plurality ofprocessors, each processor coupled to a memory cache, each processorhaving a processor ID, the method comprising: receiving from anaccessing processor a request to read a memory line of the data storage;reading the memory line from the data storage; determining only from theread memory line whether the memory line stores current data, or storesthe processor ID of an owner processor holding the current data of thememory line in its memory cache by comparing a first portion of thememory line with a code that indicates that the current data is held inthe memory cache of a processor; and responsive to the determination,providing portions of the memory line to the accessing processor aseither the current data, or the processor ID of the owner processor. 23.The method of claim 22, wherein reading the memory line from the datastorage consists of a single memory access.
 24. The method of claim 22,further comprising: providing a control signal to the accessingprocessor in conjunction with the provided portions of the memory line,for indicating to the accessing processor whether the provided portionsinclude the current data or processor ID of the owner processor.
 25. Themethod of claim 22, further comprising: responsive to determining onlyfrom the read memory line that the memory line stores current data,providing the memory line to the accessing processor as data and storingin the memory line the processor ID of the accessing processor as theprocessor ID of an owner processor holding the data of the memory linein its memory cache; and responsive to determining only from the readmemory line that the memory line stores the processor ID of an ownerprocessor currently holding the current data in its memory cache,providing from the memory line the processor ID of the owner processorto the accessing processor, and storing in the memory line the processorID of the accessing processor as the processor ID of an owner processorcurrently holding the data of the memory line in its memory cache. 26.The method of claim 22, wherein providing portions of the memory line tothe accessing processor as current data, further comprises: prior toproviding the portions of the memory line, setting a portion of thememory line to an actual value of the portion held in a storage areaseparate from the memory line.
 27. The method of claim 22, furthercomprising: deriving the code from an address of the read memory line.28. The method of claim 22, wherein determining only from the readmemory line whether the memory line stores current data, or stores theprocessor ID of an owner processor holding the current data of thememory line in its memory cache, further comprises: responsive to thefirst portion of the memory line matching the code, determining from asecond portion of the memory line whether the first portion containsdata that incidentally matches the code; and responsive to the firstportion of the memory line containing data that incidentally matches thecode, retrieving current data for the second portion, and setting thesecond portion of the memory line to the current data prior to providingthe portions of the memory line to the accessing processor as thecurrent data.
 29. A method of managing memory access to a data storagein a multi-processor system including a plurality of processors, eachprocessor coupled to a memory cache, each processor having a processorID, the method comprising: receiving from an accessing processor arequest to access a memory line of the data storage; reading the memoryline from the data storage; responsive to the request being a request toread the memory line: determining only from the read memory line whetherthe memory line stores current data, or stores the processor ID of anowner processor holding the current data of the memory line in itsmemory cache by comparing a first portion of the memory line with a codethat indicates that the current data is held in the memory cache of aprocessor; and responsive to the determination, providing portions ofthe memory line to the accessing processor as either the current data,or the processor ID of the owner processor; and responsive to therequest being a request to write data to the memory line: determiningonly from the read memory line whether the accessing processor ID is anowner processor holding the current data of the memory line in itsmemory cache, or is another processor; and responsive to the accessingprocessor being the owner processor, writing the current data to thememory line.
 30. The method of claim 29, wherein reading the memory linefrom the data storage consists of a single memory access.
 31. A memorycircuit for managing memory access to a data storage in amulti-processor system including a plurality of processors, eachprocessor coupled to a memory cache, each processor having a processorID and coupled to a data bus, the memory circuit comprising: a datastorage comprising a plurality of memory lines, each memory line adaptedto store a plurality of data words; a memory controller adapted toaccess a memory line in the data storage in response to a request froman accessing processor, and further adapted to: receive from anaccessing processor a request to read a memory line of the data storage;read the memory line from the data storage; determining only from theread memory line whether the memory line stores current data, or storesthe processor ID of an owner processor holding the current data of thememory line in its memory cache by comparing a first portion of thememory line with a code that indicates that the current data is held inthe memory cache of a processor; and responsive to the determination,provide portions of the memory line to the accessing processor via thedata bus as either the current data, or the processor ID of the ownerprocessor.
 32. The memory circuit of claim 31, wherein the memorycontroller is adapted to read the memory line from the data storage in asingle memory access.
 33. The memory circuit of claim 31, furthercomprising: a control bus that couples the memory controller to theplurality of processors; and the memory controller is further adapted toprovide a control signal to the accessing processor via the control busin conjunction with the provided portions of the memory line on the databus, for indicating to the accessing processor whether the providedportions include the current data or processor ID of the ownerprocessor.
 34. The memory circuit of claim 31, wherein the memorycontroller is further adapted to: responsive to determining only fromthe read memory line that the memory line stores current data, providethe memory line to the accessing processor as data via the data bus andstoring in the memory line the processor ID of the accessing processoras the processor ID of an owner processor holding the data of the memoryline in its memory cache; and responsive to determining only from theread memory line that the memory line stores the processor ID of anowner processor currently holding the current data in its memory cache,provide from the memory line the processor ID of the owner processor tothe accessing processor as data via data bus, and store in the memoryline the processor ID of the accessing processor as the processor ID ofan owner processor currently holding the data of the memory line in itsmemory cache.
 35. The memory circuit of claim 31, wherein the memorycontroller is further adapted to: prior to providing the portions of thememory line via the data bus to the accessing processor, set a portionof the memory line to an actual value of the portion held in a storagearea separate from the memory line.
 36. The memory circuit of claim 31,wherein the memory controller is further adapted to: derive the codefrom an address of the read memory line.
 37. The memory circuit of claim31, wherein in determining only from the read memory line whether thememory line stores current data, or stores the processor ID of an ownerprocessor holding the current data of the memory line in its memorycache, the memory controller is adapted to: responsive to the firstportion of the memory matching the code, determine from a second portionof the memory line whether the first portion contains data thatincidentally matches the code; and responsive to the first portion ofthe memory containing data that incidentally matches the code, retrievecurrent data for the second portion, and setting the second portion ofthe memory to the current data prior to providing the portions of thememory line to the accessing processor as the current data.
 38. A memorycircuit for managing memory access to a data storage in amulti-processor system including a plurality of processors, eachprocessor coupled to a memory cache, each processor having a processorID and coupled to a data bus, the memory circuit comprising: a datastorage comprising a plurality of memory lines, each memory line adaptedto store a plurality of data words; a memory controller adapted toaccess a memory line in the data storage in response to a request froman accessing processor, and further adapted to: receive from anaccessing processor a request to access a memory line of the datastorage; read the memory line from the data storage; responsive to therequest being a request to read the memory line: determining only fromthe read memory line whether the memory line stores current data, orstores the processor ID of an owner processor holding the current dataof the memory line in its memory cache by comparing a first portion ofthe memory line with a code that indicates that the current data is heldin the memory cache of a processor; and responsive to the determination,provide portions of the memory line to the accessing processor via thedata bus as either the current data, or the processor ID of the ownerprocessor; responsive to the request being a request to write data tothe memory line: determine only from the read memory line whether theaccessing processor ID is an owner processor holding the current data ofthe memory line in its memory cache, or is another processor; andresponsive to the accessing processor being the owner processor, writingthe current data to the memory line.
 39. The memory circuit of claim 38,wherein the memory controller is adapted to read the memory line fromthe data storage in a single memory access.
 40. The memory circuit ofclaim 38, further comprising: a control bus that couples the memorycontroller to the plurality of processors; and the memory controller isfurther adapted to provide a control signal to the accessing processorvia the control bus in conjunction with the provided portions of thememory line on the data bus, for indicating to the accessing processorwhether the provided portions include the current data or processor IDof the owner processor.
 41. A multiprocessor system, comprising: aplurality of processors, each processor coupled to a memory cache, eachprocessor having a processor ID; a bus coupled to each of theprocessors, and adapted to transmit requests from the processors fordata stored in a memory and data stored in the memory to the processors;a memory, coupled to the bus, and comprising: a data storage comprisinga plurality of memory lines, each memory line adapted to store aplurality of data words, each memory line including: a) a first portionthat can be either: i) a code for indicating that the data words of thememory line are currently held in the memory cache of one of theprocessors, or ii) data for processing; and b) a second portion that canbe either: i) the processor ID of an owner processor currently holdingthe data words from the memory line in its memory cache; or ii) data forprocessing; a memory controller adapted to access a memory line in thedata storage in response to a request from an accessing processor, andfurther adapted to: i) if the first portion does not contain the code,then provide the first and second portions of the memory line as data tothe accessing processor via the bus, store the code in the first portionof the memory line, and store the processor ID of the accessingprocessor in the second portion of the memory line as the processor IDof an owner processor; and ii) if the first portion contains the code,then provide the processor ID of the owner processor from the secondportion of the memory line to the accessing processor via the bus, andstore the processor ID of the accessing processor in the second portionof the memory line as the owner processor.
 42. The system of claim 41,wherein: each memory line further includes a third portion adapted tostore a bit indicating whether the first portion contains the code orcontains data; and the data storage includes a storage area separatefrom the memory lines, that stores for each memory line, a correspondingdata field holding the actual bit value of the third portion of thememory line; wherein the memory controller is further adapted to: iii)if the first portion contains the code and the third portion stores abit indicating that the first portion contains data, set the thirdportion to the actual bit value stored in the data field correspondingto the memory line, provide the first, second, and third portions of thememory line to the accessing processor via the bus, store the code inthe first portion of the memory line, and store the processor ID of theaccessing processor in the second portion of the memory line as theprocessor ID of the owner processor.
 43. A multiprocessor system,comprising: a) a plurality of processors, each processor coupled to amemory cache, each processor having a processor ID; b) a bus coupled toeach of the processors, and adapted to transmit requests from theprocessors for data stored in a memory and data stored in the memory tothe processors; c) a memory, coupled to the bus, and comprising: 1 ) adata storage comprising: a) a plurality of memory lines, each memoryline adapted to store a plurality of data words, each memory lineincluding: i) a first portion that can be either: a first code forindicating that the data words of the memory line are currently held inthe memory cache of one of the processors, or data for processing by oneof the processors; and ii) a second portion that can be either: theprocessor ID of an owner processor currently holding the data words fromthe memory line in its memory cache; or data for processing; iii) athird portion that can be either: an owned code indicating that thememory line is data; data for processing; b) a storage area separatefrom the memory lines, and including for each memory line acorresponding data field that stores an actual data value of the thirdportion of the memory line; 2 ) a memory controller adapted to access amemory line in the data storage in response to a read request from anaccessing processor, and further adapted to: i) if first portion doesnot contain the first code, then provide the memory line to theaccessing processor, set the accessing processor as the owner processorby storing the processor ID in the second portion, and store a new codein the first portion; ii) if the first portion does contain the code andthe third portion does not stores the owned code, set the third portionof the memory line to the actual value of the third portion stored inthe corresponding data field in the separate storage area, the providethe first, second, and third portions of the memory line to theaccessing processor as data, set the accessing processor as the ownerprocessor by storing the processor ID of the accessing processor in thesecond portion of the memory line, and store the first code in the firstportion of the memory line; and iii) if the first portion does containfirst code and the third portion does store then owned code, and theaccessing processor is not the owner processor, then provide theaccessing processor with the processor ID of the owner processor fromthe second portion of the memory line, and set the accessing processoras the owner processor by storing the processor ID of the accessingprocessor in the second portion of the memory line.
 44. A multiprocessorsystem, comprising: a) a plurality of processors, each processor coupledto a memory cache, each processor having a processor ID; b) a buscoupled to each of the processors, and adapted to transmit requests fromthe processors for data stored in a memory and data stored in the memoryto the processors; c) a memory, coupled to the bus, and comprising: 1 )a data storage comprising: a) a plurality of memory lines, each memoryline adapted to store a plurality of data words, each memory lineincluding: a first portion that can be either: i) a first code forindicating that the data words of the memory line are currently held inthe memory cache of one of the processors, or ii) data for processing byone of the processors; and a second portion that can be either: i) theprocessor ID of an owner processor currently holding the data words fromthe memory line in its memory cache; or ii) data for processing; a thirdportion that can be either: i) an owned code indicating that the memoryline is data; ii) data for processing; b) a storage area separate fromthe memory lines, and including for each memory line a correspondingdata field that stores an actual data value of the third portion of thememory line; 2 ) a memory controller adapted to access a memory line inthe data storage in response to a write request from an accessingprocessor, and further adapted to: if the first portion contains thefirst code, the third portion stores the owned code, and the secondportion stores the processor ID of the accessing processor, storeupdated data words from the accessing processor in the memory line; andif the first portion contains the first code, the third portion storesthe owned code, and the second portion stores the processor ID of anon-requesting processor, then perform no update on the memory line, inorder to prevent the memory line from storing invalid data.